The present invention relates to a phase-change memory device, and more particularly, to a technology for reducing current consumption occurring in the process of selecting memory cells according to address, and performance deterioration caused due to line load.
Among various memory devices, a dynamic random access memory (DRAM), used as a computer main memory device, is capable of random access and high integration at a low cost. However, the DRAM has a drawback of being a volatile memory. Meanwhile, a NAND flash memory, which is a nonvolatile memory, is capable of high integration at a low cost and is advantageous in terms of power consumption. However, the NAND flash memory has a low operating speed since it is incapable of random access.
A phase-change random access memory (PCRAM) device is an example of various memory devices that have been developed to overcome the drawbacks of such conventional memory devices. The PCRAM device is capable of random access and high integration at a low cost as a nonvolatile memory. That is, the PCRAM device processes data as fast as volatile memories and retains data even in a power-off state.
The PCRAM device stores data using a phase changeable material. The PCRAM device is a nonvolatile memory device that uses a phase change of a phase changeable material depending on the temperature conditions, where a resistance changes proportional to the phase change.
FIG. 1 is a circuit diagram illustrating a structure of a conventional phase-change memory cell.
The phase-change memory cell includes a diode D and a variable resistor R which are connected to a word line WL and a bit line BL, respectively. It is controlled by control signals transferred through the word line WL and the bit line BL.
To write/read data to/from the phase-change memory cell, a control signal activated to a logic low level is transferred through the word line to the phase-change memory cell. Since a potential level of the word line WL becomes low, the phase-change memory cell has current flow from the bit line BL to the word line WL through the diode D.
In a write operation, current, the amount of which depends on the logic level of data to be written, is provided through the bit line by a write driver. (A typical write driver is well known to those skilled in the art and thus, detailed description thereof is omitted.) Accordingly, the resistance of the variable resistor R is determined according to the logic level of data. In a read operation, current, which flows from the bit line BL to the word line WL, is sensed by a bit line sense amplifier. (A typical bit line sense amplifier is well known to those skilled in the art and detailed description thereof is omitted.) Since the resistance of the variable resistor R has a different value according to the logic level of data stored in the phase-change memory cell, the stored data can be distinguished between logic low/high data by sensing the current.
FIG. 2 is a block diagram of a conventional phase-change memory device to illustrate a process of selecting a word line and a bit line according to address.
Hereinafter, it is assumed that 512 word lines and 512 bit lines are allocated per cell matrix MAT and 64 cell matrixes MAT (8 rows*8 columns) exist.
First of all, a row operation to select a corresponding word line is described. Among eight row selection signals XBLK<0:7>, corresponding one, e.g., a first row selection signal XBLK<0> is activated by decoding a first row address XADD<0:2> by a row block selecting unit 210. In response to the activated first row selection signal XBLK<0>, a first word line decoding unit 220_0 is enabled while other word line decoding units 220_1 to 220_7 (omitted in drawings as being the same as the first word line decoding unit) are disabled.
The enabled first word line decoding unit 220_0 receives and decodes a second row address XADD<3:8> to activate one of 64 global row signals GX. The 64 global row signals GX are inputted to local row switch units 230_0 to 230_7 (some omitted in drawings as being the same as the other ones) each provided with 512 word lines WL. Accordingly, the global row signals GX are each allocated eight word lines WL.
When one of the global row signals GX is activated, corresponding eight word lines WL are connected to eight current lines CL while 504 other word lines WL are not connected to the eight current lines CL in each cell matrix MAT. The eight current lines CL are coupled to enabling units 240_0 to 240_7 (some omitted in drawings as being the same as the other ones). The enabling units 240_0 to 240_7 select one of the eight current lines CL belonging thereto in response to a third row address XADD<9:11> and ground the selected current line CL. Accordingly, a potential level of one word line WL is activated to a logic low level in each cell matrixes MAT.
Explaining a column operation to select a corresponding bit line, corresponding one of eight column selection signals YBLK<0:7>, e.g., a first column selection signal YBLK<0> is activated by decoding a first column address YADD<0:2> by a column selecting unit 250. In response to the activated first column selection signal YBLK<0>, a first SA (sense amplifier)/WD (write driver) array unit 260_0 is enabled while other SA/WD array units 260_1 to 260_7 are disabled. The enabled first SA/WD array unit 260_0 receives and decodes a second column address YADD<3:8> to drive one of 64 global bit lines GBL.
Meanwhile, column pre-decoding units 270_0 to 270_7 (some omitted in drawings as being the same as the other ones) decode a third column address YADD<9:11> to output eight pre-decode signals PDEC<0:7>. Local column switch units 280_0 to 280_7 (some omitted in drawings as being the same as the other ones) connect the global bit lines GBL to corresponding local bit lines BL in response to the pre-decode signals PDEC<0:7>. Among 512 local bit lines BL provided in each cell matrix MAT, 64 local bit lines BL are connected to 64 corresponding global bit lines GBL (1:8 coding) by the local column switch units 280_0 to 280_7.
Actually, since one global bit line GBL in cell matrixes MAT0, 8, 16, 24, 32, 40, 48 and 56 is driven by the first SA/WD array unit 260_0 as described above, one local bit line BL in the corresponding cell matrixes is driven. As a result, eight local bit lines BL are driven at the same time and data is processed in one memory cell since one word line WL is selected in the cell matrix MAT0 according to the row operation described above.
To write/read data to/from phase-change memory cells, a relatively high voltage is used. A plurality of word lines WL and a plurality of bit lines BL are driven to select a phase-change memory cell and write/read data to/from it, as described above. Accordingly, line load is relatively greater than other memory devices in the phase-change memory device, where the line load causes current consumption. Therefore, the technology development is required to prevent excess current consumption and performance deterioration due to line load.